7 lines
21 KiB
Plaintext
7 lines
21 KiB
Plaintext
const lang = Object.freeze({ "displayName": "SystemVerilog", "fileTypes": ["sv", "SV", "v", "V", "svh", "SVH", "vh", "VH"], "name": "system-verilog", "patterns": [{ "begin": "\\s*\\b(function|task)\\b(\\s+automatic)?", "beginCaptures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "keyword.control.systemverilog" } }, "end": ";", "name": "meta.function.systemverilog", "patterns": [{ "captures": { "1": { "name": "storage.type.systemverilog" }, "2": { "name": "entity.name.function.systemverilog" } }, "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*\\s+)?([a-zA-Z_][a-zA-Z0-9_:]*)\\s*(?=\\(|;)" }, { "include": "#port-dir" }, { "include": "#base-grammar" }] }, { "captures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "keyword.control.systemverilog" }, "3": { "name": "entity.name.function.systemverilog" } }, "match": "\\s*\\b(task)\\s+(automatic)?\\s*(\\w+)\\s*;", "name": "meta.task.simple.systemverilog" }, { "begin": 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}, "2": { "name": "keyword.operator.systemverilog" }, "3": { "name": "keyword.sva.systemverilog" } }, "match": "\\b(\\w+)\\s*(:)\\s*(assert)\\b" }, { "begin": "\\s*(//)\\s*(psl)\\s+((\\w+)\\s*(:))?\\s*(default|assert|assume)", "beginCaptures": { "0": { "name": "meta.psl.systemverilog" }, "1": { "name": "comment.line.double-slash.systemverilog" }, "2": { "name": "keyword.psl.systemverilog" }, "4": { "name": "entity.psl.name.systemverilog" }, "5": { "name": "keyword.operator.systemverilog" }, "6": { "name": "keyword.psl.systemverilog" } }, "end": ";", "name": "meta.psl.systemverilog", "patterns": [{ "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge)\\b", "name": "keyword.psl.systemverilog" }, { "include": "#operators" }, { "include": "#functions" }, { "include": "#constants" }] }, { "begin": "\\s*(/\\*)\\s*(psl)", "beginCaptures": { "0": { "name": "meta.psl.systemverilog" }, "1": { "name": "comment.block.systemverilog" }, "2": { "name": "keyword.psl.systemverilog" } }, "end": "(\\*/)", "endCaptures": { "1": { "name": "comment.block.systemverilog" } }, "name": "meta.psl.systemverilog", "patterns": [{ "captures": { "0": { "name": "meta.psl.systemverilog" }, "2": { "name": "entity.psl.name.systemverilog" }, "3": { "name": "keyword.operator.systemverilog" }, "4": { "name": "keyword.psl.systemverilog" } }, "match": "^\\s*((\\w+)\\s*(:))?\\s*(default|assert|assume)" }, { "captures": { "1": { "name": "keyword.psl.systemverilog" }, "2": { "name": "entity.psl.name.systemverilog" } }, "match": "\\b(asset|cover)\\s+(property)\\s+(\\w+)" }, { "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge|negedge)\\b", "name": "keyword.psl.systemverilog" }, { "include": "#operators" }, { "include": "#functions" }, { "include": "#constants" }] }, { "captures": { "1": { "name": "keyword.other.systemverilog" } }, "match": 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"include": "#all-types" }, { "include": "#operators" }, { "include": "#port-dir" }, { "match": "\\b(and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\\b", "name": "support.type.systemverilog" }, { "include": "#strings" }, { "match": "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b", "name": "support.function.systemverilog" }, { "captures": { "1": { "name": "storage.type.systemverilog" }, "2": { "name": "keyword.operator.cast.systemverilog" } }, "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)(')(?=\\()", "name": "meta.cast.systemverilog" }, { "captures": { "1": { "name": "keyword.other.systemverilog" }, "2": { "name": "constant.other.systemverilog" } }, "match": "^\\s*(localparam|parameter)\\s+([A-Z_][A-Z0-9_]*)\\b\\s*(?=(=))", "name": "meta.param.systemverilog" }, { "captures": { "1": { "name": "keyword.other.systemverilog" } }, "match": "^\\s*(localparam|parameter)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b\\s*(?=(=))", "name": "meta.param.systemverilog" }, { "captures": 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"\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=\\[[a-zA-Z0-9_\\-\\+]*:[a-zA-Z0-9_\\-\\+]*\\]\\s+[a-zA-Z_][a-zA-Z0-9_\\s]*)" }, { "captures": { "1": { "name": "support.type.systemverilog" }, "3": { "name": "support.type.scope.systemverilog" }, "4": { "name": "keyword.operator.scope.systemverilog" }, "5": { "name": "storage.type.interface.systemverilog" } }, "match": "\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=[a-zA-Z_][a-zA-Z0-9_\\s]*)" }, { "match": "\\s*\\b(output|input|inout|ref)\\b", "name": "support.type.systemverilog" }] }, "storage-modifier-systemverilog": { "match": "\\b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\\b", "name": "storage.modifier.systemverilog" }, "storage-scope-systemverilog": { "captures": { "1": { "name": "support.type.systemverilog" }, "2": { "name": "keyword.operator.scope.systemverilog" } }, "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)(::)", "name": "meta.scope.systemverilog" }, "storage-type-systemverilog": { "patterns": [{ "match": "\\s*\\b(var|wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|integer|int|longint|shortint|logic|bit|byte|shortreal|string|time|realtime|real|process|void)\\b", "name": "storage.type.systemverilog" }, { "match": "\\s*\\b(uvm_transaction|uvm_component|uvm_monitor|uvm_driver|uvm_test|uvm_env|uvm_object|uvm_agent|uvm_sequence_base|uvm_sequence|uvm_sequence_item|uvm_sequence_state|uvm_sequencer|uvm_sequencer_base|uvm_component_registry|uvm_analysis_imp|uvm_analysis_port|uvm_analysis_export|uvm_config_db|uvm_active_passive_enum|uvm_phase|uvm_verbosity|uvm_tlm_analysis_fifo|uvm_tlm_fifo|uvm_report_server|uvm_objection|uvm_recorder|uvm_domain|uvm_reg_field|uvm_reg|uvm_reg_block|uvm_bitstream_t|uvm_radix_enum|uvm_printer|uvm_packer|uvm_comparer|uvm_scope_stack)\\b", "name": "storage.type.uvm.systemverilog" }] }, "strings": { "patterns": [{ "begin": '"', "beginCaptures": { "0": { "name": "punctuation.definition.string.begin.systemverilog" } }, "end": '"', "endCaptures": { "0": { "name": "punctuation.definition.string.end.systemverilog" } }, "name": "string.quoted.double.systemverilog", "patterns": [{ "match": "\\\\.", "name": "constant.character.escape.systemverilog" }, { "match": "(?x)%\n (\\d+\\$)? # field (argument #)\n [#0\\- +']* # flags\n [,;:_]? # separator character (AltiVec)\n ((-?\\d+)|\\*(-?\\d+\\$)?)? # minimum field width\n (\\.((-?\\d+)|\\*(-?\\d+\\$)?)?)? # precision\n (hh|h|ll|l|j|t|z|q|L|vh|vl|v|hv|hl)? # length modifier\n [bdiouxXhHDOUeEfFgGaACcSspnmt%] # conversion type\n ", "name": "constant.other.placeholder.systemverilog" }, { "match": "%", "name": "invalid.illegal.placeholder.systemverilog" }] }] }, "struct-anonymous": { "begin": "\\s*\\b(struct|union)\\s*(packed)?\\s*", "beginCaptures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "keyword.control.systemverilog" } }, "end": "(})\\s*([a-zA-Z_]\\w*)\\s*;", "endCaptures": { "1": { "name": "keyword.operator.other.systemverilog" } }, "name": "meta.struct.anonymous.systemverilog", "patterns": [{ "include": "#base-grammar" }] } }, "scopeName": "source.systemverilog" });
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var systemVerilog = [
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lang
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];
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export { systemVerilog as default };
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