7 lines
21 KiB
Plaintext
7 lines
21 KiB
Plaintext
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const lang = Object.freeze({ "displayName": "SystemVerilog", "fileTypes": ["sv", "SV", "v", "V", "svh", "SVH", "vh", "VH"], "name": "system-verilog", "patterns": [{ "begin": "\\s*\\b(function|task)\\b(\\s+automatic)?", "beginCaptures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "keyword.control.systemverilog" } }, "end": ";", "name": "meta.function.systemverilog", "patterns": [{ "captures": { "1": { "name": "storage.type.systemverilog" }, "2": { "name": "entity.name.function.systemverilog" } }, "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*\\s+)?([a-zA-Z_][a-zA-Z0-9_:]*)\\s*(?=\\(|;)" }, { "include": "#port-dir" }, { "include": "#base-grammar" }] }, { "captures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "keyword.control.systemverilog" }, "3": { "name": "entity.name.function.systemverilog" } }, "match": "\\s*\\b(task)\\s+(automatic)?\\s*(\\w+)\\s*;", "name": "meta.task.simple.systemverilog" }, { "begin": "\\s*\\b(typedef\\s+(struct|enum|union)\\b)\\s*(packed)?\\s*([a-zA-Z_][a-zA-Z0-9_]*)?", "beginCaptures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "keyword.control.systemverilog" }, "3": { "name": "keyword.control.systemverilog" }, "4": { "name": "storage.type.systemverilog" } }, "end": "(})\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*;", "endCaptures": { "1": { "name": "keyword.operator.other.systemverilog" }, "2": { "name": "entity.name.function.systemverilog" } }, "name": "meta.typedef.struct.systemverilog", "patterns": [{ "include": "#struct-anonymous" }, { "include": "#base-grammar" }] }, { "captures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "entity.name.declaration.systemverilog" } }, "match": "\\s*\\b(typedef\\s+class)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\s*;", "name": "meta.typedef.class.systemverilog" }, { "begin": "\\s*\\b(typedef)\\b", "beginCaptures": { "1": { "name": "keyword.control.systemverilog" } }, "end": "([a-zA-Z_][a-zA-Z0-9_]*)\\s*(?=(\\[[a-zA-Z0-9_:\\$\\-\\+]*\\])?;)", "endCaptures": { "1": { "name": "entity.name.function.systemverilog" } }, "name": "meta.typedef.simple.systemverilog", "patterns": [{ "captures": { "1": { "name": "storage.type.userdefined.systemverilog" }, "2": { "name": "keyword.operator.param.systemverilog" } }, "match": "\\b([a-zA-Z_]\\w*)\\s*(#)\\(", "name": "meta.typedef.class.systemverilog" }, { "include": "#base-grammar" }, { "include": "#module-binding" }] }, { "begin": "\\s*(module)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b", "beginCaptures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "entity.name.type.module.systemverilog" } }, "end": ";", "endCaptures": { "1": { "name": "entity.name.function.systemverilog" } }, "name": "meta.module.systemverilog", "patterns": [{ "include": "#port-dir" }, { "match": "\\s*(parameter)", "name": "keyword.other.systemverilog" }, { "include": "#base-grammar" }, { "include": "#ifmodport" }, { "match": "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b", "name": "support.function.systemverilog" }] }, { "captures": { "1": { "name": "keyword.control.systemverilog" }, "2": { "name": "entity.name.function.systemverilog" } }, "match": "\\b(sequence)\\s+([a-zA-Z_][a-zA-Z0-9_]*)", "name": "meta.sequence.systemverilog" }, { "captures": { "1": { "name": "keyword.control.systemverilog" } }, "match": "\\b(bind)\\s+([a-zA-Z_][a-zA-Z0-9_\\.]*)\\b" }, { "captures": { "0": { "name": "meta.section.begin.systemverilog" }, "1": { "name": "keyword.other.block.systemverilog" }, "3": { "name": "keyword.operator.systemverilog" }, "4": { "name": "entity.name.section.systemverilog" } }, "match": "\\s*(begin|fork)\\s*((:)\\s*([a-zA-Z_][a-zA-Z0-9_]*))\\b", "name": "meta.definition.systemverilog" }, { "captures": { "1": { "name": "keyword.sva.systemverilog" }, "2": { "name": "entity.name.sva.systemverilog" } }, "match": "\\b(asset|cover)\\s(property)\\s+(\\w+)" }, { "captures": { "1": { "name": "entity.name.sva.systemverilog" }, "2": { "name": "keyword.operator.systemverilog" }, "3": { "name": "keyword.sva.systemverilog" } }, "match": "\\b(\\w+)\\s*(:)\\s*(assert)\\b" }, { "begin": "\\s*(//)\\s*(psl)\\s+
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var systemVerilog = [
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lang
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];
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export { systemVerilog as default };
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